Optimal Performance and Power Efficiency for Hyperscale, Telecom, Networking, and Infrastructure Edge Devices The Arm Neoverse N3…
- CPU
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
Optimal Performance and Power Efficiency for Hyperscale, Telecom, Networking, and Infrastructure Edge Devices The Arm Neoverse N3…
32-bit RISC-V microcontroller.
64-bit RISC-V embedded core with in-order single issue pipeline
64-bit RISC-V embedded core with in-order single issue pipeline.
32-bit RISC-V embedded core with in-order single issue pipeline
32-bit RISC-V embedded core with in-order single issue pipeline.
The second-generation high-performance RISC-V CPU delivers a major leap in compute capability, designed for deployment across dat…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
Low-Power Deeply Embedded RISC-V Processor
The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core.
Infrastructure for Next-Generation Throughput Demands The Neoverse E1 processor is a new class of efficient CPU technology design…
A Revolution in High Performance Computing The Neoverse V1 CPU is designed to deliver per-core performance on demanding HPC, HPC …
Industry- Performance and Power Efficiency for Cloud-to-Edge Infrastructure Our first Armv9 infrastructure CPU, Neoverse N2 offer…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
An interpolating filter chain, numerically controlled oscillator, and mixer comprise the DUC.
Ultra-Low-Power Deeply Embedded RISC-V Processor
The BA51 is a configurable, low-power, deeply embedded RISC-V processor IP core.
1:4 Fixed Length Visually Lossless Compression/Decompression
Suppressing the degradation of image quality by the original comp./decomp.
H8SX CPU subsystem (H8SX C3000) IP
H8SX is a high speed 32-bit CPU, which is upward-compatible with H8/300, H8/300H and H8S CPUs on an object level.
H8S CPU subsystem (H8S C200) IP
H8S is a high speed 16-bit CPU with an internal 32-bit architecture, which is upward-compatible with H8/300 and H8/300H CPUs on a…
H8/300 CPU IP ( 8-bit CPU IP )
H8/300 is a high speed 8-bit CPU with an internal 16-bit architecture.
32-bit Embedded RISC-V Functional Safety Processor
The EMSA5-FS is a processor core designed for functional safety.
NPU IP for AI Vision and AI Voice
The VIP9000 family offers programmable, scalable and extendable solutions for markets that demand real time and low power AI devi…
U54 MC Multicore: four U54 cores and one S51 core
The SiFive U54-MC Standard Core is the world's first RISC-V application processor, capable of supporting full-featured operating …