U54 MC Multicore: four U54 cores and one S51 core
The SiFive U54-MC Standard Core is the world's first RISC-V application processor, capable of supporting full-featured operating …
Overview
The SiFive U54-MC Standard Core is the world's first RISC-V application processor, capable of supporting full-featured operating systems such as Linux.
The U54-MC has 4x 64-bit U5 cores and 1x 64-bit S5 core - providing high performance with maximum efficiency. This core is an ideal choice for low-cost Linux applications such as IoT nodes and gateways, storage, and networking.
Key features
- Fully compliant with the RISC-V ISA specification
- 4x RV64GC U54 Application Cores
- 32KB L1 I-cache with ECC
- 32KB L1 D-cache with ECC
- 8 Region Physical Memory Protection
- 48 Local Interrupts per core
- Sv39 Virtual Memory support with 38 Physical Address bits
- 1x RV64IMAC S51 Monitor Core
- 16KB L1 I-Cache with ECC
- 8KB DTIM with ECC
- 8 Region Physical Memory Protection
- 48 Local Interrupts
- Fully Coherent TileLink Bus
- Integrated 2MB L2 Cache with ECC
- Real-time capabilities
- Both the L1 Instruction Cache and the L2 Cache can be configured into high speed deterministic SRAMs
- CLINT for multi-core timer and software interrupts
- PLIC with support for up to 511 interrupts with 7 priority levels
- Debug with instruction trace
- U54 Performance
- 2.87/1.7 DMIPS/MHz (Best Effort/Legal)
- 2.75 CoreMark/MHz
Block Diagram
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about CPU IP cores
What is U54 MC Multicore: four U54 cores and one S51 core?
U54 MC Multicore: four U54 cores and one S51 core is a CPU IP core from Sifive, Inc. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.