Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
SOQPSK-TG LDPC Modulator for communication systems with non-linear amplifiers
The IPrium-SOQPSK-LDPC-Modulator IP Core implements constant amplitude CPM SOQPSK modulation with LDPC Coding.
16-ACS Multi Function Viterbi Decoder
The VA08VB is a medium complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
Efficiently supports front-end audio processing like beamforming and noise reduction, as well as neural network-assisted speech r…
100 Gbit/s Polar Encoder and Decoder with soft-decision LLR input
The IPrium-100-Gbps-Polar-Encoder-Decoder IP Core implements Successive Cancellation Polar forward error correction algorithm wit…
CCSDS 231.0 LDPC(128, 64) and LDPC(512, 256) Encoder and Decoder
The IPrium-LDPC-CCSDS-231-Encoder-Decoder IP Core implements Low Density Parity Check (LDPC) forward error correction algorithm f…
The MIMO Decoder accepts two independent input streams, and the channel estimation matrix.
CCSDS AR4JA LDPC Decoder & Encoder
The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding diff…
CCSDS AR4JA LDPC Encoder/Decoder
AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, …
LDPC corrects errors caused by flash storage failure mechanisms.
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizab…
Kalman Filter hardware accelerator
The eSi-Kalman core provides hardware acceleration for Kalman Filtering (KF) and related target tracking algorithms, such as meas…
High performance FFT optimised for Radar
A configurable efficient pipelined radix-2 squared FFT with additional functionality making it optimised for point cloud generati…
The IntelliProp IPC-BL119A-ZM is a configurable IP core that provides a method of extending an information block with extra bits …
The K-best decoder is part of the MIMO decoder.
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.
The LTE Lite PHY supplied as a portable and synthesizable Verilog-2001 IP.
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps …
The K-best decoder is part of the MIMO decoder.