Getting your Zynq SoC design up and running using PlanAhead
Adam Taylor, EADS Astrium
EETimes (2/8/2013 11:22 AM EST)
The Zynq-7000 All Programmable SoC is the first of a new class of Xilinx devices that marry a dual-core ARM Cortex-A9 processor with programmable logic on a single chip. As such, the device offers a great leap forward in not only system flexibility, but also performance and integration. This system-on-chip platform does, however, require the FPGA engineer to consider a slightly different development path than is customary for logic-based FPGAs.
The good news is that development is not as difficult as you might think, thanks in large part to the availability of the Xilinx PlanAhead tool. Let’s take a closer look at the steps involved in generating a Zynq-7000 system that you can load via JTAG.
To read the full article, click here
Related Semiconductor IP
- Xilinx Virtual Cable
- 25 Gb/s AES-ECB 128/192/256 Crypto Cores
- Xilinx HMC Controller
- Xilinx MicroBlaze Trace Core (XMTC)
- Xilinx Ultra Scale Plus SATA HOST IP
Related Articles
- Agile Verification for SoC Design
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- Low Power Design in SoC Using Arm IP
- Multi Voltage SoC Power Design Technique
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM