Tutorial: Improving the transient immunity of your microcontroller-based embedded design - Part 2
By Ross Carlton, Freescale Semiconductor, Inc.
Nov 17 2006 (9:15 AM), Embedded.com
The hardware design techniques employed for an application will establish the baseline immunity performance. The purpose of hardware techniques is to reduce the level or frequency content of immunity signals below that needed to cause performance degradation or long-term microcontroller (MCU) reliability problems.
Hardware techniques should be maximized to ensure desired electromagnetic compatibility (EMC) performance before attempting any software techniques. This is important because software techniques do not reduce the level of immunity signals to which the MCU is exposed " they only reduce the impact of these signals on system operation. Even though the application performance may not be degraded, exposure to immunity signals can adversely affect long-term reliability.
In order to produce an application that meets both the mandated EMC requirements and minimizes cost, the design process must be both methodical and iterative. Rigorous system and PCB design methodologies are required to ensure quality and consistency in the design process. Without such methodologies, achieving EMC compliance will be accidental and unrepeatable. The design process must also be iterative to ensure the best possible system design and PCB layout at the lowest cost.
A design that minimizes cost cannot be completed properly in one pass " regardless of the quality of personnel or tools. An EMC-compliant, low-cost application is the result of close and consistent collaboration between the EMC engineer and all other engineering disciplines (i.e. " electrical engineers, mechanical engineers, PCB layout engineers, etc).
Nov 17 2006 (9:15 AM), Embedded.com
The hardware design techniques employed for an application will establish the baseline immunity performance. The purpose of hardware techniques is to reduce the level or frequency content of immunity signals below that needed to cause performance degradation or long-term microcontroller (MCU) reliability problems.
Hardware techniques should be maximized to ensure desired electromagnetic compatibility (EMC) performance before attempting any software techniques. This is important because software techniques do not reduce the level of immunity signals to which the MCU is exposed " they only reduce the impact of these signals on system operation. Even though the application performance may not be degraded, exposure to immunity signals can adversely affect long-term reliability.
In order to produce an application that meets both the mandated EMC requirements and minimizes cost, the design process must be both methodical and iterative. Rigorous system and PCB design methodologies are required to ensure quality and consistency in the design process. Without such methodologies, achieving EMC compliance will be accidental and unrepeatable. The design process must also be iterative to ensure the best possible system design and PCB layout at the lowest cost.
A design that minimizes cost cannot be completed properly in one pass " regardless of the quality of personnel or tools. An EMC-compliant, low-cost application is the result of close and consistent collaboration between the EMC engineer and all other engineering disciplines (i.e. " electrical engineers, mechanical engineers, PCB layout engineers, etc).
To read the full article, click here
Related Semiconductor IP
- 6.5V ESD Clamp in 180nm Technology
- ESD diode and Clamps for 90nm TSMC G/GT/LP
- Stand alone ESD diode for TSMC .13u Foundry Process
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
- TSMC 2nm 1V8 ESD Local Clamp – Low Leakage
Related Articles
- Guide to VHDL for embedded software developers: Part 2 - More essential commands
- Improving ASIP code generation and back-end compilation: Part 2
- Designing with ARM Cortex-M based SoC Achitectures: Part 2 - Some typical applications
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 2
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection