A system-level verification flow for EDA
Mike Stellfox, Cadence Design Systems
(03/19/2007 9:00 AM EDT), EE Times
The EDA industry continues to innovate and develop cutting-edge tools for the design and verification of hardware. But it has not yet found a way to accelerate growth within hardware/ software development or to capitalize on the interest around what Cadence calls enterprise system-level (ESL) solutions.
To create a solution that offers a true enterprisewide system-level flow, the industry must develop a comprehensive methodology that leverages much of the success we've seen in hardware development. This includes focusing on system-level creation, simulation, transformation, analysis, integration and verification. With continued innovation in those areas, focusing on how they relate to system-level development, we'll gain the power and flexibility needed to deliver on the vision of system-level verification.
(03/19/2007 9:00 AM EDT), EE Times
The EDA industry continues to innovate and develop cutting-edge tools for the design and verification of hardware. But it has not yet found a way to accelerate growth within hardware/ software development or to capitalize on the interest around what Cadence calls enterprise system-level (ESL) solutions.
To create a solution that offers a true enterprisewide system-level flow, the industry must develop a comprehensive methodology that leverages much of the success we've seen in hardware development. This includes focusing on system-level creation, simulation, transformation, analysis, integration and verification. With continued innovation in those areas, focusing on how they relate to system-level development, we'll gain the power and flexibility needed to deliver on the vision of system-level verification.
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