A system-level verification flow for EDA
Mike Stellfox, Cadence Design Systems
(03/19/2007 9:00 AM EDT), EE Times
The EDA industry continues to innovate and develop cutting-edge tools for the design and verification of hardware. But it has not yet found a way to accelerate growth within hardware/ software development or to capitalize on the interest around what Cadence calls enterprise system-level (ESL) solutions.
To create a solution that offers a true enterprisewide system-level flow, the industry must develop a comprehensive methodology that leverages much of the success we've seen in hardware development. This includes focusing on system-level creation, simulation, transformation, analysis, integration and verification. With continued innovation in those areas, focusing on how they relate to system-level development, we'll gain the power and flexibility needed to deliver on the vision of system-level verification.
(03/19/2007 9:00 AM EDT), EE Times
The EDA industry continues to innovate and develop cutting-edge tools for the design and verification of hardware. But it has not yet found a way to accelerate growth within hardware/ software development or to capitalize on the interest around what Cadence calls enterprise system-level (ESL) solutions.
To create a solution that offers a true enterprisewide system-level flow, the industry must develop a comprehensive methodology that leverages much of the success we've seen in hardware development. This includes focusing on system-level creation, simulation, transformation, analysis, integration and verification. With continued innovation in those areas, focusing on how they relate to system-level development, we'll gain the power and flexibility needed to deliver on the vision of system-level verification.
To read the full article, click here
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related Articles
- EDA focus shifts to system level design
- Accurate System Level Power Estimation through Fast Gate-Level Power Characterization
- HW/SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures
- The Challenges and Benefits of Analog/Mixed-Signal and RF System Verification above the Transistor Level
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities