Putting the system in electronic system design
Ken Karnofsky, The MathWorks
(02/04/2008 9:00 AM EST), EE Times
You've heard it before. Increasingly complex systems and technologies like multicore processors and FPGAs have rendered old design methodologies obsolete. New approaches are needed: system-level abstractions that handle complexity, and tools that automate the costly, time-consuming steps between concept and implementation.
Within the realm of processor-centric system-on-chip design and verification, electronic system-level (ESL) methods aim to address some of the problems. Various approaches and commercial tools have been introduced (and others repackaged) since EDA analyst Gary Smith coined the term ESL several years ago. The tools enable hardware designers to model complex SoC architectures, permitting software developers to start writing code before hardware is available, and in some cases aiding hardware component implementation.
But the narrow scope of most ESL approaches and tools has limited their adoption. A more encompassing methodology, one that steps beyond the SoC, is needed to slash time, cost and errors in complex system development. The new methodology should:
(02/04/2008 9:00 AM EST), EE Times
You've heard it before. Increasingly complex systems and technologies like multicore processors and FPGAs have rendered old design methodologies obsolete. New approaches are needed: system-level abstractions that handle complexity, and tools that automate the costly, time-consuming steps between concept and implementation.
Within the realm of processor-centric system-on-chip design and verification, electronic system-level (ESL) methods aim to address some of the problems. Various approaches and commercial tools have been introduced (and others repackaged) since EDA analyst Gary Smith coined the term ESL several years ago. The tools enable hardware designers to model complex SoC architectures, permitting software developers to start writing code before hardware is available, and in some cases aiding hardware component implementation.
But the narrow scope of most ESL approaches and tools has limited their adoption. A more encompassing methodology, one that steps beyond the SoC, is needed to slash time, cost and errors in complex system development. The new methodology should:
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- Emerging Trends and Challenges in Embedded System Design
- Understanding LTTPR: Enabling High-Speed DisplayPort Interconnects in Complex System Designs
- Software Architecture for IP verification in Operating System environment
- SpiritEd: A Register Specification System integrating IP-XACT and Adobe FrameMaker
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM