Synchronizing sample clocks of a data converter array

Kazim Peker and Altug Oz, Analog Devices, Inc.
EDN (June 29, 2016)

The requirements of higher system bandwidth and resolution in a variety of applications from communications infrastructure to instrumentation drive up the demand for connecting multiple data converters in an array form. Designers must find low noise and high accuracy solutions to clock and synchronize a large array of data converters using the common JESD204B serial data converter interface.

Clock generation devices containing jitter attenuation functions, internal VCOs, and a multitude of outputs and many synchronization management functions, are now coming to market to address this system problem. In many real-life applications, however, the sheer number of required clocks in a data converter array exceeds what may be feasible to obtain from a single IC component. Designers often resort to connecting multiple clock generation and clock distribution components together, thus, creating a broad “clock tree”.

This article provides a real-life case study of how to build a flexible and re-programmable clock expansion network, that maintains not only an excellent phase noise/jitter performance, but also passes-on the required synchronization information from the 1^st device of the clock tree to the last one with deterministic control.