Sub-Threshold Design - A Revolutionary Approach to Eliminating Power
Mike Salas, VP Marketing, Ambiq Micro
EDN (December 22, 2014)
Low energy consumption has replaced performance as the foremost challenge in electronic design. Performance is important, but it must now accede to the energy capacity of batteries and even the minimal output of energy harvesters. Performance at all costs no longer works; energy consumption is now the dominant requirement. While reducing energy consumption is critically important throughout the electronics industry, the question is: how should that goal be achieved? Ambiq Micro’s approach moves beyond the incremental improvements that other semiconductor companies have taken and makes revolutionary advances through a unique approach to the problem: sub-threshold circuit design.
Energy is consumed in two fundamental ways: as leakage, when a circuit’s state isn’t changing, and dynamically as internal nodes are charged up and down. For realistic circuits in operation, dynamic power dominates – especially for the higher power supply voltages used in most designs today.
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Articles
- Deliver "Smarter" Faster: Design Methodology for AI/ML Processor Design
- Improving design routability and timing by smart port reduction and placement technique
- The Gatekeeper of a Successful Design is the Interconnect
- How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities