Simplifying AC and DC data acquisition signal chains
By Wasim Shaikh, Srikanth Nittala (Analog Devices)
embedded.com (August 12, 2020)
Sampling phenomena in analog-to-digital converters (ADCs) induce the problems of aliasing and capacitive kickback, and to solve these problems, designers use filters and driving amplifiers that introduce their own sets of challenges. This makes achieving precision dc and ac performance in medium bandwidth application areas a challenge and designers end up trading off system goals to do so.
This article describes continuous-time sigma-delta (∑-Δ) ADCs that inherently and dramatically solve the sampling problems by simplifying signal chains. They remove the need for antialiasing filters and buffers, and solve signal chain offset errors and drift issues associated with the additional components. These benefits shrink the solution size, ease solution design, and improve the phase matching and overall latency of the system. This article also draws a comparison with discrete-time converters and highlights system benefits, as well as the constraints of using continuous-time sigma-delta ADCs.
To read the full article, click here
Related Semiconductor IP
- Sigma-Delta ADC
- 10Bit 25MHz sigma-delta ADC for VT sensor on SMIC 40nm
- Rad-hard 17-bit 3-channel sigma-delta ADC at 3.2kS/s
- 180nm 13-bit Sigma-Delta ADC
- The GF40SLPV25_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver amplifier, and audio PLL to support a wide range of sample rates.
Related Articles
- Data acquisition systems and SoCs - A guide
- Design trade-offs of using SAR and Sigma Delta Converters for Multiplexed Data Acquisition Systems
- Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security
- A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection