Rotten to the Core — Part 2: Soft and Vanilla or Hard and Cryptic?
byDr. Barry Henderson
Introduction
In Part 1 of my article about IP core development, I explored the basic ideas and processes involved in selecting an IP core vendor. We looked into how to reduce risk, how to write the Lore (the requirements specification) that spells out all the major technical details required to design the core, and how to pick a reliable developer. Part 2 now takes a look under the hood, by which I mean that now we want to explore how a core is developed. This includes aspects of responsibility, the various types of core deliverables, verification environments, and steps to take to verify what you get, and how to stay on track once a project is under way.
Read more....Related Semiconductor IP
- Ultra Ethernet MAC & PCS 100G/200G/400G/800G
- Ethernet PCS 100G/200G/400G/800G/1.6T
- Ethernet MAC 100G/200G/400G/800G/1.6T
- Junction Over-Temperature Detector with Linear Centigrade-to-Voltage Output - X-FAB XT018
- Performance P570 Gen 3
Related Articles
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- How to Elevate RRAM and MRAM Design Experience to the Next Level
- NoCs and the transition to multi-die systems using chiplets
- The Hitchhiker's Guide to Programming and Optimizing CXL-Based Heterogeneous Systems
Latest Articles
- Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
- TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing
- Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA
- A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
- ObfAx: Obfuscation and IP Piracy Detection in Approximate Circuits