Reduce Time to Market for FPGA-Based Communication and Datacenter Applications
Joe Mallet, Synopsys
EETimes (9/13/2017 03:50 PM EDT)
As FPGA-based realizations become bigger and more complex, synthesis tools that deliver an automated flow are the obvious choice for creating optimized designs in a timely manner.
The market is changing for FPGAs due to advancements in low power, high performance, and lower cost, all of which are increasing FPGA adoption into datacenter applications like network switches, CPUs, and network acceleration.
The growing need for FPGAs in these types of applications is being driven by the fact that they can achieve the desired processing throughput and latency requirements. With increasing amounts of data to process from very large data sets, FPGAs are a good fit to handle the acceleration required by these types of applications. While the flexibility of FPGAs is an advantage for FPGA designers, it also poses challenges in that -- in addition to the hardware -- the designers must implement the drivers, software, and application layers for these applications. Furthermore, they will need to achieve the best quality of results (QoR) for performance and area, accelerated runtimes, and deep debug to help accelerate system design and get to the market quickly.
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Articles
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
- Methodology to reduce Run Time of Timing/Functional Eco
- A Time for Rebalancing Global Patent Strategies in the Semiconductor Market?
- Generative AI for Analog Integrated Circuit Design: Methodologies and Applications
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities