Bridging the Gap between Pre-Silicon Verification and Post-Silicon Validation in Networking SoC designs
Dr. Lauro Rizzatti, Verification Consultant
EETimes (8/15/2016 01:55 PM EDT)
De-risking complex networking SoC development is no longer a remote objective; rather, it is available to all design teams today.
Recently, I've been writing a series of articles on the benefits of using hardware emulation for verifying networking system-on-chip (SoC) designs ahead of silicon availability. In this column, I wish to describe a new approach to bridge the gap between the pre-silicon verification and the post-silicon validation of the same networking designs.
In order to set the stage, let's highlight the trends in this highly competitive market segment. The massive adoption of software-driven networking (SDN) architectures has been driven by the upsurge of new markets, such as cloud computing, big datacenters, and mobile. Figure 1 charts the SDN market trend in revenues, which are anticipated to grow by 135% over the next two years.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Articles
- ARM intrusive debugging for post-silicon SoC validation
- Networking driver strategies for using embedded Linux
- Networking software key to PICMG 2.16 optimization
- SoC silicon is first-time success following simulation and validation of novel array processor
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST