PSL Verification Package for the Open Core Protocol
By Sami Maisniemi, Nokia
December 14, 2006 -- edadesignline.com
Introduction
Nokia utilizes the Open Core Protocol (OCP) as a standard interconnection architecture for its systems. So far there has not been a unified verification methodology for interconnections available. As a consequence, there was an obvious demand for a new verification package that fulfills the following requirements:
December 14, 2006 -- edadesignline.com
Introduction
Nokia utilizes the Open Core Protocol (OCP) as a standard interconnection architecture for its systems. So far there has not been a unified verification methodology for interconnections available. As a consequence, there was an obvious demand for a new verification package that fulfills the following requirements:
- The package verifies the compatibility of the interconnection with the OCP standard.
- The package can be installed with minimal efforts without modifying the existing verification environment.
- The package can be configured with minimal efforts without access to the source code.
- The package is compatible with the existing design and verification flows.
- No previous knowledge of assertion-based verification or hardware property languages is required.
- No additional EDA tools are required.
- The package must be cost-effective in terms of maintenance and support.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Articles
- IP core-centric communications protocol Introducing Open Core Protocol 2.0
- Better Products, Happier Customers with Current-Based Simulation/Verification and the Open Core Protocol
- Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
- SIMT-Aware Lockstep Verification and Functional-Coverage Closure Methodology for an Open-Source RISC-V GPGPU: A UVM 1.2 Environment
Latest Articles
- Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
- A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
- An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC
- A Formal Security Analysis of CAN XL
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience