PSL Verification Package for the Open Core Protocol
By Sami Maisniemi, Nokia
December 14, 2006 -- edadesignline.com
Introduction
Nokia utilizes the Open Core Protocol (OCP) as a standard interconnection architecture for its systems. So far there has not been a unified verification methodology for interconnections available. As a consequence, there was an obvious demand for a new verification package that fulfills the following requirements:
December 14, 2006 -- edadesignline.com
Introduction
Nokia utilizes the Open Core Protocol (OCP) as a standard interconnection architecture for its systems. So far there has not been a unified verification methodology for interconnections available. As a consequence, there was an obvious demand for a new verification package that fulfills the following requirements:
- The package verifies the compatibility of the interconnection with the OCP standard.
- The package can be installed with minimal efforts without modifying the existing verification environment.
- The package can be configured with minimal efforts without access to the source code.
- The package is compatible with the existing design and verification flows.
- No previous knowledge of assertion-based verification or hardware property languages is required.
- No additional EDA tools are required.
- The package must be cost-effective in terms of maintenance and support.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- IP core-centric communications protocol Introducing Open Core Protocol 2.0
- Better Products, Happier Customers with Current-Based Simulation/Verification and the Open Core Protocol
- Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs