Practical Power Network Synthesis For Power-Gating Designs
Kaijian Shi, Zhian Lin, Yi-Min Jiang, Synopsys, Inc.
(06/05/2007 3:00 AM EDT), EE Times
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.
This method simultaneously optimizes the number and positions of sleep transistors and the power network's grids and wires for minimum area, maximum routeability with a given IR-drop target. With this automated method for synthesizing the power network, you can more easily take advantage of power gating to reduce leakage power consumption dramatically in SoCs.
(06/05/2007 3:00 AM EDT), EE Times
Although methodologies for power network synthesis typically assume that design tools can freely size sleep transistors for power gating, this assumption does not hold up for real-world SoC designs where the sleep transistors are commonly designed as custom switch cells of fixed sizes. The method described in this article avoids this unrealistic assumption and introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.
This method simultaneously optimizes the number and positions of sleep transistors and the power network's grids and wires for minimum area, maximum routeability with a given IR-drop target. With this automated method for synthesizing the power network, you can more easily take advantage of power gating to reduce leakage power consumption dramatically in SoCs.
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