Power management ICs: meeting new design paradigm challenges
Jae-Inh Song, Dongbu HiTek Co., Ltd.
10/30/2010 11:15 PM EDT
Power management semiconductor market forecast
Power management ICs (PMIC) represents one of the fastest-growing semiconductor market segments. According to iSuppli, the total available power management market is expected to reach $31.4 billion worldwide in 2010 and then more than double by 2014, reaching $45 billion, posting a 15% compound annual growth rate (CAGR), Figure 1. Revenue generated by PMICs is expected to grow from $12.4 billion in 2009 to $19.7 billion in 2014, posting a 14.5% CAGR.

Figure 1: Revenue forecast for PMICs, 2009 â 2014 (in billions of U.S. dollars)
The design paradigm for power management ICs (PMICs) continues to shift from analog-heavy implementations to system-on-chip solutions using digital techniques. Key factors driving this transition are increasing multi-functionality, particularly in consumer electronics and mobile applications, as well as severe pricing pressures to make products affordable and the need for faster turnaround from silicon prototype to shipment of finished ICs. As a result of these factors, chip design and development at smaller geometries has escalated dramatically.
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