Planning reset strategy: Flow & functionality in OVC
Parag Goel, Pushkar Naik, Applied Micro Circuits Corp.
3/9/2011 8:01 AM EST
Overview
Reset strategy, which has long been a part and parcel of the design methodology, playing a vital role in the successful working of any given design, has become increasingly important on the verification methodology front. Reset forms a fundamental property of any protocol/system and is the first step in the sequence of operations done for any system bring up. The following write-up addresses this essential strategy to be followed during verification using an OVM-based test bench.
While developing an OVM–based IP (i.e. OVM Verification Component (OVC)), it is required to get a clear perspective on the way it behaves and recovers from reset application during the course of simulation.
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