OTP firmware enhances processor flexibility
Yeng Peng
(02/20/2006 10:00 AM EST), EE Times
Processor firmware must be upgradable to account for new algorithms or to simplify the development of derivative products. Storing such firmware in ROM or flash memory poses problems for embedded applications. With mask-programmable ROM, the processor's firmware is "locked in" during chip fabrication. In a typical system-on-chip design flow, firmware is directly in the project's critical path. Every change in the contents of a masked ROM requires an NRE charge and a turnaround that may stretch to months. ROM-based storage also increases the cost of inventory management.
Flash memory is prohibitively costly for many consumer applications. Accessing firmware stored on external flash is power-intensive compared with storing the firmware on-chip. Downloading firmware from an external flash chip makes the download process susceptible to undesirable interception by an unauthorized third party. On-chip flash, through reverse-engineering, can also be read to reveal its contents.
A better solution is to embed one-time programmable (OTP) nonvolatile memory on the processing chip. Beyond accommodating changes in data standards and decreasing the time and cost of derivative products, OTP memory can handle engineering change orders through software modifications. Product lifetime is increased, and firmware configuration during system development enhances the co-development of hardware and software.
To read the full article, click here
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- OTP with a ROM Conversion Option Provides Flexibility and Cost Savings for On-Chip Microcode Storage
- High-Performance DSPs -> Voice control enhances appliance apps
- High-Performance DSPs -> Reconfigurable coprocessors create flexibility in DSP apps
- MPEG Standards -> Object-based MPEG offers flexibility
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection