Case study: optimizing PPA with RISC-V custom extensions in TWS earbuds

By John Min, Andes Technology
embedded.com (August 11, 2022)

A look at using custom extensions in a RISC-V processor to enable power, performance and area (PPA) optimized true wireless stereo earbuds SoC design.

A common goal for many IC designs is achieving an optimum combination of power, performance, and area (PPA). This article examines the components and design of a currently shipping true wireless stereo (TWS) chip design, indicating the engineering tradeoffs made to achieve the PPA demanded by the final ear buds. In particular, we will also look at the RISC-V ISA (instruction set architecture) extensions that helped to dramatically reduce power while achieving the desired performance at no extra cost.

A TWS chip is mostly a Bluetooth RF transceiver. It comprises a 128-tap finite impulse response (FIR) filter, 128-tap least means square (LMS) adaptive filter, an active noise control (ANC)

hybrid function and the computational elements and buses needed to compute these functions. In this design, the first three of the four elements would require the greatest amount of computing resource: The FIR filter will demand 1,693 instruction cycles, the LMS filter another 1,820 cycles, and the ANC function, a whopping 10,404 cycles. The system block diagram illustrates the major components of the TWS design with analog functions on the left and digital on the right. The Bluetooth transceiver (top left) consists of an RF baseband controller and 64kbytes of exchange memory. The transceiver and audio subsystem below are complex because the TWS design has two independently operating speakers and microphones. The phase lock loop (PLL) for each must be synchronized to ensure each is running at the same frequency.

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