A nuts and bolts engineering approach to using open source IP
By Girish Managoli, MindTree
Embedded.com (01/25/10, 06:49:00 PM EST)
In the world of product development, time-to-market keeps shrinking and demand for better quality keeps growing. Open Source, which is often thought to be the definitive solution to meet both objectives - faster development cycle and better quality, is on the mind of many OEMs and product companies.
In reality, the companies find it difficult to overcome the FUD (Fear, Uncertainty and Doubt) to make a final decision and say, "Yes, we will use open source in our product."
In the product development process, at the one end are the engineering people - developers, architects, engineering managers - who are aware of open source and its benefits, but lack the power to take decisions. At the other end, are the management and the legal people, who can take decisions, but may not have sufficient ground-up information. How do we bridge this gap? How can the engineering team convince the management to boldly embrace open source?
In this article I will go over some key factors and guidelines to consider with respect to the use open source in product engineering. The objective is for us, the engineering people, to be prepared with sufficient and solid information to convince our management and legal departments to take that final call with confidence.
To read the full article, click here
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related Articles
- Post-Quantum Cryptography: Why Open Source alone is Not Enough for Secure IP Deployment
- Successful Use of an Open Source Processor in a Commercial ASIC
- Open Source FlexRay Communication: Time Triggered OS and FlexRay Communication Middleware
- Open source in consumer electronics: What, why and how
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities