On hardware dependencies and scrum
Mike Hogg, Zuhlke
embedded.com (January 22, 2014)
Embedded systems require hardware. We've experienced successful hardware development following agile principles, in particular by ASIC and FPGA teams. Nevertheless, many hardware engineers find it impossible to follow an agile approach; their "design -- manufacture -- assemble -- test" lifecycle is often too long and expensive for such an iterative incremental scheme. How can agile software developers work with such hardware engineers?
Let's focus on running a scrum process when there are inter-dependencies with a non-agile team. Advice on managing this scenario is rare.
Agile teams work on user stories that describe the functionality to be delivered. These are collected in a product backlog. Should user stories only cover software features? No, in the embedded space software alone is insufficient to make a product. Rather, we can use top level stories (known as epics) that reflect the combined software and hardware development needed, and are understood by both disciplines. The software team will likely break these epics down in to a series of smaller constituent user stories for the software features, while the hardware team may manage their work differently.
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Articles
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans
- HW/SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures
- Practical Case: Embedded Multiprocessor Design on a Flexible Hardware: NEO_CORE_CYCLONE_III
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities