Viewpoint: Need to move beyond the network-on-chip
Ray Brinks, Vice President, Engineering, Sonics, Inc.
EE Times (01/04/2010 2:49 PM EST)
Over the last decade, designers have been content with standard connectivity methodologies to fulfill the needs of their system-on-chip (SoC) designs.
With today's design starts using 65nm design rules or smaller, the number of cores in an SoC can exceed 100. Connecting 50 or 100 cores breeds challenges that SoC design teams did not have to previously face.
The inherent communications between on-chip cores is now taking on more of the comprehensive characteristics of a network rather than simply a bus. These characteristics include standard interface protocols, sockets at the edge of the network to allow cores to maintain a level of independence, and scalability so that the network can grow or shrink as needed. Enter the network-on-chip (NoC).
To read the full article, click here
Related Semiconductor IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
- NoC Interconnect IP Generator
- AXI NoC Non-Coherent Mesh
- FlexGen Smart Network-on-Chip (NoC) IP
- NoC System IP
Related Articles
- Concepts and Implementation of the Philips Network-on-Chip
- A comparison of Network-on-Chip and Busses
- A Central Caching Network-on-chip Communication Architecture Design
- Synthesizable Switching Logic For Network-On-Chip Designs on 90nm Technologies
Latest Articles
- GSPIM: A Temporal-Locality-Aware 4D Gaussian Splatting Accelerator with Polymorphic PIM and Multi-Frame Rendering Dataflow
- Memory Admission and Result-Retention Sizing in an RV32IMC FPGA Soft Processor
- A Cross-Domain Matrix Engine for Signal Processing and Deep Neural Net Inference
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors