Using multi-bit flip-flop custom cells to achieve better SoC design efficiency

Gourav Kapoor, Gaurav Gupta, and Nalin Gupta, Freescale Semiconductor
embedded.com (August 20, 2014)

System-on-chip (SoC) designs are becoming more and more complex, by whatever means you measure it: power domains, gate count, packing densities, heat dissipation capacities, etc. At such high packing densities, it has become more challenging for physical design teams to make practical trade-offs in performance, power consumption, and die area. More robust techniques and circuit elements are needed to strike the best balance between these elements. In general, the three elements are complimentary, with controlling power and area usually resulting in higher performance.

However, keeping power and area under control in today’s high performance designs is a challenge, and power in particular is a major area of concern with the advent of lower technology nodes and increased packing densities.

New techniques are being developed to bring the best out of a design in terms of all these parameters. One such technique is the design of custom complex cells. In this paper, we will be discussing the architecture of one of the most commonly used complex cells - multi-bit flip-flops - and its merits and drawbacks. Later in this paper we will discuss the results of implementation using multi-bit flops in a particular design and what you need to be concerned about.

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