Mission Critical in Auto SoC: Interconnect IP
Kurt Shuler, VP Marketing, Arteris
EETimes (10/22/2016 08:00 AM EDT)
The average number of IP cores integrated into automotive SoCs is growing from about 20 today to more than 100 within the next five to ten years.
Today, the automobile industry is a key driver for technology innovation much like the mobile industry propelled growth in earlier part of the new millennium.
While the market for electronics in cars is relatively small in comparison to the mobile industry today, the growth rate is higher, which makes it all the more compelling for the next generation of SoC designs.
Much like the mobile industry before it, the growth in capabilities and features for automotive electronic systems is driving the transition from microcontrollers to ever more sophisticated microprocessors in ever more complex SoCs.
Application areas are expanding from engine control units into Advanced Driver Assistance Systems (ADAS), self-driving systems with over-the-air updating capabilities, active safety systems, infotainment systems and more.
In particular, ADAS are driving up the semiconductor bill-of-materials (BOM) in automobiles due to the requirements for advanced processing and sensing. Figure 1 below provides a breakdown for the growing semiconductor revenue as automation increases in cars.
To read the full article, click here
Related Semiconductor IP
- DFI 6.0 Verification IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
Related Articles
- NoC Interconnect Fabric IP Improves SoC Power, Performance and Area
- How to manage changing IP in an evolving SoC design
- Why network-on-chip IP in SoC must be physically aware
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
Latest Articles
- Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
- Hardware-managed heterogeneous high-bandwidth memory and flash in LLM inference systems
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework