Don't Let Metastability Cause Problems in Your FPGA-Based Design
By Jennifer Stephenson, Altera Corp.
pldesignline.com (September 29, 2009)
Metastability is a phenomenon that can cause system failure in digital devices such as FPGAs, when a signal is transferred between circuitry in asynchronous clock domains. This article describes metastability in FPGAs, explains why the phenomenon occurs, and discusses how it can cause design failures. The calculated mean time between failures (MTBF) due to metastability indicates whether designers should take steps to reduce the chance of such failures. This article also explains how MTBF is calculated from design and device parameters, and presents techniques to improve system reliability with increased MTBF.
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