Mergers create two tiers of IP providers
Mergers create two tiers of IP providers
By Ian Cameron, EE Times UK
April 17, 2002 (2:42 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020417S0050
LONDON A two-tiered semiconductor intellectual-property (IP) vendor market may be emerging as a result of recent mergers and acquisitions in the sector. Gartner Dataquest analyst Jim Tully said mergers between vendors such as Parthus Technologies and DSP Group's Ceva division are sharpening the divide between the top players and the rest of the market. Though such deals would not automatically lead to further short-term industry consolidation, Tully said they could amplify other factors driving consolidation. "There are a large number of IP companies in the market say, 150," he said. "Most of them are very small businesses and some specialize in real niche application areas." Most work with big companies as virtual members of design teams. If they "address niche, not commodity, markets, small vendors can plod on," Tully said. Still, uncertainty is rampant in the sector. "If the small companies go out of busine ss, the big ones could be in trouble," he said. "That's one of the forces suggesting there would be more consolidation." Tully said he does not expect to see wholesale consolidation until 2006 or '07. Given that Parthus is scaling down development of its in-house DSP core, Tully said he expected it to eventually stop selling the Ceva core separately or embedding it in its platform. The market for microprocessor and DSP cores is "getting a bit crowded," he added. "Quite a lot [of chip makers] have developed DSP cores and would prefer not to carry on supporting them internally."
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Rapid Validation of Post-Silicon Devices Using Verification IP
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
- Time Interleaving of Analog to Digital Converters: Calibration Techniques, Limitations & what to look in Time Interleaved ADC IP prior to licensing
- Create high-performance SoCs using network-on-chip IP
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety