Memory fault models and testing
Abhilash Kaushal, Freescale
EDN (June 29, 2015)
A different set of fault models and testing techniques is required for memory blocks vs. logic. MBIST algorithms that are used to detect faults inside memory are based upon these fault models. This article discusses different types of memory fault models.
Memory fault models – Single cell faults
Stuck at (SAFs): Stuck at faults in memory is the one in which the logic value of a cell (or line in the sense amplifier or driver) is always 0 or 1.

Left: Write operation state diagram of a good memory cell; Right: State diagram for s-a-0 and s-a-1 memory cell
Transition Faults (TFs): In transition faults a cell fails to make a (0 to 1) transition or a (1 to 0) transition when it is written; up transition fault is denoted as <0w1/0/- > and a down transition fault is denoted as < 1w0/1/- >

State diagram for transition faults
Write destructive faults (WDFs): A non transition write operation in a memory cell causes the cell to flip. There are two types of Write destructive faults:
1) Memory cell in state 0, write 0 on it. Cell becomes 1. Denoted as <0w0/1/->
2) Memory cell in state 1, write 1 on it. Cell becomes 0.Denoted as <1w1/0/->

State diagram for write destructive faults
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Verifying embedded software functionality: fault localization, metrics and directed testing
- Accurate memory models for all
- Memory Testing - An Insight into Algorithms and Self Repair Mechanism
- Using PSS and UVM Register Models to Verify SoC Integration
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs