Library promotes common standard for design properties
Library promotes common standard for design properties
By Michael Howard, C-Cube Microsystems, EE Times
August 19, 2002 (10:38 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020815S0008
The Open Verification Library (OVL) provides a standard set of assertion modules that not only enhance simulation but also ease the adoption of RTL formal verification tools. The OVL assertion modules are written in standard HDL, so the user is not required to learn a proprietary language in order to specify design behaviors for verification. Moreover, the same assertions can be used in both simulation and in the BlackTie formal verification environment.
The automatic-check benchmark data shows that formal verification with BlackTie can be applied from the block level all the way up to full chip. Further, BlackTie's automatic checks eliminate the need to create testbenches or assertions to exhaustively verify common design functions.
The OVL is an open-source initiative, and the library can be freely downloaded from the Web (www.verificationlib.org).
The latest release, version 1.1. 0, is a set of 26 Verilog assertion monitor modules. More assertion modules will be added in the next release.
Complete documentation of the assertions in the library is provided on the OVL Web site. Because the library is user-community-extensible, anyone can add to, modify and redistribute the OVL under the terms an open-source license.
The OVL/Assertion Committee oversees changes and extensions to the OVL version posted on the Web. Users can go online to offer their opinions and suggestions to the committee, which is part of the Accellera standards organization (www.accellera.org).
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design
- Designing Low Power Standard Cell Library With Improved Drive Granularity
- Choosing the best Standard Cell Library without falling into the traps of traditional benchmarking methods
- Generative AI for Analog Integrated Circuit Design: Methodologies and Applications
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs