IP in FPGAs: Blessing and a curse
Dave Orecchio
11/22/2010 10:31 AM EST
One of the largest confabs in the still-maturing semiconductor IP industry happens next week. The IP-SoC 2010 event in Grenoble, France, has been a long-standing meeting point (19 years and counting) for those in and around the IP business. The strength of the technical sessions and the level of attendance is a tribute to the folks at Design & Reuse who started the event many years ago. While the IP industry has had its fits and starts, D&R has persevered and, with the backing of EE Times/UBM, appears to have validated the need for the type of service they offer (in addition to putting on the IP-SoC event). And, if imitation is the sincerest form of flattery, then Cadence, through its Chip Estimate offering, has reinforced that validation of the market need for IP infrastructure such as listing and evaluation services.
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