Introduction to USB -- Part III
Christian Legare, Micrium
EETimes (12/12/2012 10:51 AM EST)
1-5 USB TOPOLOGY
USB can connect a series of devices using a tiered star topology. The key elements in USB topology are the host, hubs, and devices, as illustrated in Figure 1-16. Each node in the illustration represents a USB hub or a USB device. At the top level of the graph is the root hub, which is part of the host. There is only one host in the system. The specification allows up to seven tiers and a maximum of five non-root hubs in any path between the host and a device. Each tier must contain at least one hub except for the last tier where only devices are present. Each USB device in the system has a unique address assigned by the host through a process called enumeration (see section 1-12 on page 58 for more details on enumeration).
The host learns about the device capabilities during enumeration, which allows the host operating system to load a specific driver for a particular USB device. The maximum number of peripherals that can be attached to a host is 127, including the root hub.
To read the full article, click here
Related Semiconductor IP
- USB TYPE-C Verification IP
- USB PD Verification IP
- USB 4.0 Verification IP
- USB 3.0/3.1/3.2/SSIC Verification IP
- USB 1.0/1.1/2.0 Verification IP
Related Articles
- Introduction to USB - Part I
- An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1
- How to design secure SoCs, Part III: Secure Boot
- Time Sensitive Networking: An Introduction to TSN
Latest Articles
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience
- ZTA-Q: an Open-source RISC-V Platform for Accurate Quantized CNN Inference
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM