Free I/O: Improving FPGA clock distribution control
Kirk Jensen, Lattice Semiconductor
EETimes (1/23/2011 4:15 PM EST)
Clock signals in synchronous digital systems (such as those found in telecommunications) define when and how quickly data is moved through that system. A clock distribution network, consisting of multiple clock signals, distributes those signals from a shared point to all of the components in the system requiring clocked data. Because the clock signals perform a critical system function, it is clear that more attention should be given not only to the clock’s characteristics (i.e. Skew and Jitter), but also to the components that comprise the clock distribution network.
FPGA development teams are consistently challenged by overly burdensome, complex clock networks. Various factors, including increasing demand for I/O, cost reduction opportunities and the need to reduce PCB design changes, are forcing another look at those clock networks. This article examines FPGA clock distribution control challenges that are motivating development teams to change the way they design, and offers practical advice for designers who are considering ways to enable additional FPGA I/O, or improve clock network performance, by reducing the size of their clock distribution network.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Optimizing clock tree distribution in SoCs with multiple clock sinks
- Improve FPGA communications interface clock jitters with external PLLs
- Control an FPGA bus without using the processor
- Resets in FPGA & ASIC control and data paths
Latest Articles
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration
- CTTE: An Open Dual-Protocol RISC-V Trace Encoder for N-Trace and E-Trace