High-Level Synthesis - Ready for prime-time?
Maneesh Soni, Texas Instruments, Inc., Jack Erickson, Cadence Design Systems, Inc.
EETimes (11/23/2010 7:51 PM EST)
For about two decades, hardware designers have been trying to use high-level synthesis (HLS) tools. The primary goal of high-level synthesis tools has been to increase design and verification productivity by raising the level of abstraction and by defining the architectures using less code. In addition, the idea is to also reduce complexity and the number of bugs introduced due to human-error, increase simulation speed, and facilitate exploration of alternative micro-architecture choices.
This article describes the work done at Texas Instruments (TI) to research the suitability of the latest generation of HLS tools for hardware design. Particularly, the analysis is focused on C-to-Silicon Compiler from Cadence Design Systems. The findings will interest RTL designers and architects who might be considering adoption of HLS tools, methodologies, and flows.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- How High-Level Synthesis Can Raise the Efficiency of Design Reuse
- High-level synthesis, verification and language
- The future is High-Level Synthesis
- Building a NAND flash controller with high-level synthesis
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs