High-Level Synthesis - Ready for prime-time?
Maneesh Soni, Texas Instruments, Inc., Jack Erickson, Cadence Design Systems, Inc.
EETimes (11/23/2010 7:51 PM EST)
For about two decades, hardware designers have been trying to use high-level synthesis (HLS) tools. The primary goal of high-level synthesis tools has been to increase design and verification productivity by raising the level of abstraction and by defining the architectures using less code. In addition, the idea is to also reduce complexity and the number of bugs introduced due to human-error, increase simulation speed, and facilitate exploration of alternative micro-architecture choices.
This article describes the work done at Texas Instruments (TI) to research the suitability of the latest generation of HLS tools for hardware design. Particularly, the analysis is focused on C-to-Silicon Compiler from Cadence Design Systems. The findings will interest RTL designers and architects who might be considering adoption of HLS tools, methodologies, and flows.
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