Multisite, collaborative hardware design calls for HCM
Ravi Poddar (IDT) and Srinath Anantharaman (ClioSoft)
EE Times (11/16/2009 12:01 AM EST)
Software configuration management (SCM) systems have been used by software teams for decades to manage development, improve collaboration and coordinate releases. We posit that there is a need for a hardware configuration management (HCM) system that incorporates the features of SCM systems while addressing the needs of different hardware design flows.
A hardware engineer works with a design object, such as schematic, symbol or layout. The design tool usually saves this data as a collection of inter-related files. To complicate matters, the list of files that make up an object may change as modifications are made to the object, making it impossible to manage the object as separate files.
To maintain the integrity of the data, the HCM system should be able to support revision control of such composite objects. All the files that make up a composite object should be managed together as a single object within the system.
To read the full article, click here
Related Semiconductor IP
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
Related Articles
- Hardware Configuration Management and why it's different than Software Configuration Management
- IP Configuration Management with Abstract Parameterizations
- Ensuring software quality & reliability with configuration & change management
- A new approach to hardware design project management
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing