Handling Asynchronous Clock Groups in SDC
Sanjay Churiwala & Balachander Krishnamurthy, Xilinx
EETimes (11/15/2013 04:40 PM EST)
Introducing CDC
Most SoC designs in today's world employ multiple clocks and commonly have many clock domains. As data crosses from one clock domain to another within the design, the potential for metastability problems arises due to asynchronous clock domain crossings (CDCs).
Figure 1: An asynchronous crossing with simple double flop synchronization.
In Figure 1, there is an asynchronous CDC for the data going from flop F1 (clocked by C1) into F2 (clocked by C2), assuming that C1 and C2 are asynchronous with respect to each other.
To read the full article, click here
Related Semiconductor IP
- Xilinx Virtual Cable
- 25 Gb/s AES-ECB 128/192/256 Crypto Cores
- Xilinx HMC Controller
- Xilinx MicroBlaze Trace Core (XMTC)
- Xilinx Ultra Scale Plus SATA HOST IP
Related Articles
- Asynchronous Logic: large CMOS devices without a clock tree
- Ultra Low Power Designs Using Asynchronous Design Techniques (Welcome to the World Without Clocks)
- High-Performance DSPs -> DSP performance: Useful work per clock tick
- Keynoter sees asynchronous future for digital designs
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection