Giga-Scale Challenges Plague Memory Design
Zhihong Liu, CEO, ProPlus Design Solutions
EETimes (8/27/2015 00:01 AM EDT)
Advanced designs are more complex and larger than ever before and designers are balancing between accuracy and performance for large scale memory simulation and verification, fine-tuning options and settings for each circuit type
Advanced memory designers always use cutting-edge fabrication technologies for larger integration density and faster operating speed, while conserving low-power consumption. After all, memory chips are critical components that determine system performance and power.
Similarly, embedded memory IP is also the critical piece of the SoC puzzle, consuming more than 50% of the die area of a chip. No matter what type of memory IP or memory IC –– DRAM, SRAM or flash –– greater design complexity is creating massive, giga-scale challenges, which are the last thing circuit designers need or want.
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