Functional Safety and the FPGA World
Joe Mallett, Synopsys
EETimes (10/24/2016 04:40 PM EDT)
Autonomous driving is just one application example where functionally safe designs are required.
There are several trends in the industry when it comes to functional safety, along with multiple market segments utilizing the specification to help drive engineers to deliver highly reliable and safe applications to the market. In the automotive market, for example, the integration of key sub-systems into single-end devices found in the car like navigation and automated driver assistance systems (ADAS) is growing. There is a need for integrated functional safety due to the greater interaction between people, the car, and the environment. Autonomous driving is just one application example where functionally safe designs are required. FPGAs are a good fit for this application space due to their long lifetimes, high processing bandwidth, and flexibility to integrate many IP technologies.
The need for more processing creates a need for high-speed fabric and higher integration of the sub-systems into a single device, thereby pushing designs to larger devices. To facilitate building functionally safe designs, robust synthesis tools that support defined methods are needed.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related Articles
- Functional Safety for Control and Status Registers
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Developing FPGA applications for Edition 2 of the IEC 61508 Safety Standard
- FPGAs & Functional Safety in Industrial Applications
Latest Articles
- ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs
- ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training
- OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
- CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
- CXL-ClusterSim: Modeling CXL-based Disaggregated Memory Cluster for Pooling and Sharing using gem5 and SST