FPGAs for prototyping - ASICs for production
By Terry Danzer, AMIS
March 28, 2006 - pldesignline.com
FPGAs are a valuable technology for designing and prototyping digital logic into medium-volume, medium-density applications. Their high unit cost, however, makes an FPGA cost-prohibitive to move into production. Several alternatives exist for taking a digital design implemented with an FPGA into production, including Structured ASICs, cell-based ICs, and gate arrays, all of which offer lower cost, higher performance, lower power consumption, and time-to-market advantages. While the thought of migrating an FPGA design into an ASIC can be overwhelming to a design team, teaming with an experienced ASIC vendor can help ease the process.
Designing a new product in an FPGA allows for design modifications to be made quickly in hardware. Once the design code is stable and the product is ready for production, a migration from an FPGA to a mid range ASIC can cut the production unit cost by one tenth. The low non-recurring engineering (NRE) charges associated with a mid-range ASIC solution coupled with a much lower unit cost make this strategy a powerful tool in achieving low overall costs, giving users a competitive cost advantage in the market.
To help ease the migration process, several items must be considered during the initial design flow. Designs are becoming larger and more complex and the use of specialized IP is now commonplace. Careful selection of IP early during the design phase is essential. In addition, developing the FPGA and ASIC in a parallel design flow will help to speed the process. Finally, planning for portability to an ASIC from the beginning of the project will help to speed time-to-market and decrease costs (Fig 1).
March 28, 2006 - pldesignline.com
FPGAs are a valuable technology for designing and prototyping digital logic into medium-volume, medium-density applications. Their high unit cost, however, makes an FPGA cost-prohibitive to move into production. Several alternatives exist for taking a digital design implemented with an FPGA into production, including Structured ASICs, cell-based ICs, and gate arrays, all of which offer lower cost, higher performance, lower power consumption, and time-to-market advantages. While the thought of migrating an FPGA design into an ASIC can be overwhelming to a design team, teaming with an experienced ASIC vendor can help ease the process.
Designing a new product in an FPGA allows for design modifications to be made quickly in hardware. Once the design code is stable and the product is ready for production, a migration from an FPGA to a mid range ASIC can cut the production unit cost by one tenth. The low non-recurring engineering (NRE) charges associated with a mid-range ASIC solution coupled with a much lower unit cost make this strategy a powerful tool in achieving low overall costs, giving users a competitive cost advantage in the market.
To help ease the migration process, several items must be considered during the initial design flow. Designs are becoming larger and more complex and the use of specialized IP is now commonplace. Careful selection of IP early during the design phase is essential. In addition, developing the FPGA and ASIC in a parallel design flow will help to speed the process. Finally, planning for portability to an ASIC from the beginning of the project will help to speed time-to-market and decrease costs (Fig 1).
To read the full article, click here
Related Semiconductor IP
- Verification IP for C-PHY
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
Related Articles
- Transfer from FPGAs for prototype to ASICs for production
- CAST Provides a Functional Safety RISC-V Processor IP for Microchip FPGAs
- Seven Powerful Reasons Why Menta eFPGA Is the Clear Choice for A&D ASICs
- A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities