FPGA Design: Faster Runtimes & Increased Productivity
Joe Mallet, Synopsys
EETimes (1/13/2016 04:40 PM EST)
In order to achieve accelerated FPGA development schedules, designers require the aid of sophisticated synthesis tools.
FPGA device density is continuing to grow at approximately 2x per node, which is -- not surprisingly -- driving larger, more complex designs. This means that FPGA designers face several challenges as follows:
- Longer run times due to increasing design size and complexity.
- Achieving rapid synthesis turn-around time to integrate design changes.
- Avoiding unnecessary resynthesizing of pre-verified, static modules, like IP blocks and completed modules.
In order to achieve accelerated FPGA development schedules, while supporting increasing design sizes and complexity, designers require the aid of sophisticated synthesis tools.
To read the full article, click here
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related Articles
- Increased Verification Productivity through extensive Reuse
- Medical imaging process accelerated in FPGA 82X faster than software
- Achieving Better Productivity with Faster Synthesis
- LTE Single Carrier DFT: Faster Circuits with Reduced FPGA LUT/Register Usage
Latest Articles
- SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput
- New Number Formats for FFT IP Cores in Optical OFDM Transceivers
- Reducing Power Consumption of Embedded Dynamic Memories with ECCs
- NIFA: Nonlinear IMC enhanced FPGA for efficient ML inference
- A 32-channel event-based bio-signal analog front-end with adaptive delta and pulse frequency encoding