Floating- to fixed-point MATLAB algorithm conversion for FPGAs
By Tom Hill, Xilinx
June 04, 2007 -- dspdesignline.com
In a recent survey conducted by AccelChip Inc. (recently acquired by Xilinx), 53% of the respondents identified floating- to fixed-point conversion as the most difficult aspect of implementing an algorithm on an FPGA (Figure 1).
Figure 1. AccelChip DSP design challenges survey.
June 04, 2007 -- dspdesignline.com
In a recent survey conducted by AccelChip Inc. (recently acquired by Xilinx), 53% of the respondents identified floating- to fixed-point conversion as the most difficult aspect of implementing an algorithm on an FPGA (Figure 1).

Figure 1. AccelChip DSP design challenges survey.
Although MATLAB is a powerful algorithm development tool, many of its benefits are reduced during the fixed-point conversion process. For example, new mathematical errors are introduced into the algorithm because of the reduced precision of the fixed-point arithmetic. You must rewrite code to replace high-level functions and operators with low-level models that reflect the actual hardware macro-architecture. And simulation run times can be as much as 50 times longer. For these reasons, MATLAB, the overwhelming choice for algorithm development, is often abandoned in favor of C/C++ for fixed-point modeling.
To read the full article, click here
Related Semiconductor IP
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
- TSMC 2nm 1V8 ESD Local Clamp – Low Leakage
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
Related Articles
- Implementing floating-point algorithms in FPGAs or ASICs
- How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
- FPGAs - The Logical Solution to the Microcontroller Shortage
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
Latest Articles
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision