Fault-robust microcontrollers allow automotive technology convergence: Part 1, the nature of faults
Life is hard for today's automotive electronics MCUs (Microcontroller Units). On one side, you could have 50 or more of them are involved in airbags, brakes, chassis control, engine control, and X-by-wire applications. Deeper (and often immature) silicon technologies are used to reduce costs. New functionalities are implemented in software, so the memory and performance requirements have increased. Standardization efforts and new software architectures such AUTOSAR are driving automotive electronics towards more and more powerful CPUs. Internal buses are crowded by demanding peripherals.
On the other side, as a consequence of such increased complexity, the population of faults is increasing as well. These include:
In particular, hardware faults (systematic or random) are worsened by: The increased soft-error failure rates (i.e. cosmic rays); coupling effects and disturbances are more and more important; and intrinsic uncertainty due to model inaccuracy is a problem of new technologies.
Moreover, system complexity and use of third-party IP increase the verification gaps and software faults. If we define "robustness" as the ability to continue mission reliably despite the existence of systematic, random or malicious faults, how do you design fault-robust MCUs ?
Related Semiconductor IP
- USB-C Power Delivery IP Core
- Configurable Multi-Channel DMA Controller
- Samsung Foundry 4nm 1V8 GPIO I3C
- Root-of-Trust IP - High-Assurance Security for Advanced and Regulated Applications
- Root-of-Trust IP - Enhanced-Assurance, Configurable Security for Scalable Semiconductor Designs
Related Articles
- Automotive System & Software Development Challenges - Part 1
- Dealing with automotive software complexity with virtual prototyping - Part 1: Virtual HIL development basics
- M31 on the Specification and Development of MIPI Physical Layer
- The rise of FPGA technology in High-Performance Computing
Latest Articles
- GSPIM: A Temporal-Locality-Aware 4D Gaussian Splatting Accelerator with Polymorphic PIM and Multi-Frame Rendering Dataflow
- Memory Admission and Result-Retention Sizing in an RV32IMC FPGA Soft Processor
- A Cross-Domain Matrix Engine for Signal Processing and Deep Neural Net Inference
- LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation
- Automated Multi-Line Bug Repair Using Model Checker Aided LLMs: A Case Study on RISC-V Processors