Automotive Architectures: Domain, Zonal and the Rise of Central
By Thierry Kouthon, Rambus
EETimes (February 16, 2022)
Electronics first appeared in cars in 1968 when Volkswagen installed an electronic control unit (ECU) in the VW 1600 sedan’s engine to help control fuel injection. Today, automotive electronics are ubiquitous, controlling or assisting with every aspect of the vehicle’s operation and performance. Electronics now account for over 40 percent of a new vehicle’s total cost, having grown from just 18 percent in 2000, according to Deloitte.
Integration of computing technology into every aspect of the car has transformed how automotive OEMs approach design, engineering and manufacturing. Up until the past decade, vehicle electronics used a flat architecture where embedded ECUs operated together in a limited way. The advancement toward connected cars and AVs led to a divergence in how carmakers approached the communication architecture of a vehicle’s electronics.
Concurrently, the introduction of sensors into the vehicle architecture further accelerated the need for greater computing power to process and analyze the resulting data. These new aspects of the vehicle’s brain led to differing design philosophies toward designing modern vehicles, from the domain architecture to newer zonal and central architectures.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- The Rise of RISC-V and ISO 26262 Compliance
- The rise of FPGA technology in High-Performance Computing
- The Challenge of Automotive Hardware Security Deployment
- The complete series of high-end DDR IP solutions of Innosilicon is industry-leading and across major foundry processes
Latest Articles
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety