Extraction Challenges Grow in Advanced Nanometer IC Design
Carey Robertson, Mentor Graphics
5/29/2015 03:43 PM EDT
Successive generations of foundry process technologies enable ever-increasing design density, performance, and power savings, if only designers can deal with growing challenges.
Innovative new process features such as FinFET transistors require a significant increase in the accuracy of parasitic extraction — the creation of an accurate analog — for simulation and analysis to verify performance of the physical design. Here are some of the new extraction challenges and how tool technology has evolved to meet the new requirements.
What drives new tool requirements
Integrated circuit designers need to extract the detailed electrical properties of an IC after it has been committed to a specific physical layout so they can do static analysis and simulation to ensure the IC will function properly and meet critical performance requirements. Especially at 16nm and below, it is paramount to accurately capture the parasitic resistance and capacitance within FinFET devices, as well as the interactions between devices and the parasitics associated with interconnect wires. In addition, there are variations in the way different foundries model their FinFET devices. For example, some foundries use floating devices between the designed FinFETs, so it is important to capture coupling to the floating devices and between the main active devices. Parasitic resistance within the FinFET is also important—as the fin channel and the source-drain regions narrow, increased source-drain resistance degrades device performance.
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