Embedded test offers unique value for serial I/O
By Bill Schulze, Agilent
Aug 6, 2007 (11:01 AM), Embedded Systems Design
Although incorporating high-speed serial buses into embedded systems solves many problems, the design and validation processes differ and aren't well understood.
As technology progresses, the electronics industry continually reinvents itself. Embedded systems designers know this story well, many having developed applications across generations of evolving electronics technology and microprocessors.
Along the way, as basic hardware and software have evolved, so too have the methods for developing and debugging systems. Today, most microprocessors incorporate on-chip debug resources that enable the use of a low-cost hardware interface for development and testing. This type of debugging, called embedded test, is significantly aiding the growth of embedded systems and will make designing systems with high-speed serial I/O more efficient.
The economics of silicon is now making it possible for the electronics industry to take advantage of some of the advances made in the communications industry over the past 30 years, specifically the use of serial interfaces. As digital systems struggle to keep pace with the bandwidth of optical systems for the large-scale, high-speed data transmission, the ever-increasing need for speed and overall processing throughput has driven the evolution of parallel-bus structures to their practical limits. To gain more processing bandwidth, the PC industry is looking at high-speed serial interfaces, evidenced by the rapid growth of bus standards like PCI-Express.
As the PC industry adopts serial interfaces, these technologies are becoming more accepted and entrenched. Implementation costs start dropping, which means serial interfaces are now making in-roads into lower-cost PC products and mainstream digital products--in other words, embedded systems. Once again, we see that evolutionary process: as embedded systems and their associated microprocessors pick up the new technology, design teams must adopt new development and debug methods to take advantage of high-speed serial interfaces.
Aug 6, 2007 (11:01 AM), Embedded Systems Design
Although incorporating high-speed serial buses into embedded systems solves many problems, the design and validation processes differ and aren't well understood.
As technology progresses, the electronics industry continually reinvents itself. Embedded systems designers know this story well, many having developed applications across generations of evolving electronics technology and microprocessors.
Along the way, as basic hardware and software have evolved, so too have the methods for developing and debugging systems. Today, most microprocessors incorporate on-chip debug resources that enable the use of a low-cost hardware interface for development and testing. This type of debugging, called embedded test, is significantly aiding the growth of embedded systems and will make designing systems with high-speed serial I/O more efficient.
The economics of silicon is now making it possible for the electronics industry to take advantage of some of the advances made in the communications industry over the past 30 years, specifically the use of serial interfaces. As digital systems struggle to keep pace with the bandwidth of optical systems for the large-scale, high-speed data transmission, the ever-increasing need for speed and overall processing throughput has driven the evolution of parallel-bus structures to their practical limits. To gain more processing bandwidth, the PC industry is looking at high-speed serial interfaces, evidenced by the rapid growth of bus standards like PCI-Express.
As the PC industry adopts serial interfaces, these technologies are becoming more accepted and entrenched. Implementation costs start dropping, which means serial interfaces are now making in-roads into lower-cost PC products and mainstream digital products--in other words, embedded systems. Once again, we see that evolutionary process: as embedded systems and their associated microprocessors pick up the new technology, design teams must adopt new development and debug methods to take advantage of high-speed serial interfaces.
To read the full article, click here
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related Articles
- Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
- One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies
- From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems
- ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes
Latest Articles
- SCENIC: Stream Computation-Enhanced SmartNIC
- Agentic AI-based Coverage Closure for Formal Verification
- Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities