A brief primer on embedded SoC packaging options
Deepak Behera, Sumit Varshney, Sunaina Srivastava, and Swapnil Tiwari, Freescale Semiconductor
11/20/2011 9:16 PM EST
With shrinking technology, voltage levels are being reduced, lowering noise margins required to enable a clean design from a signal integrity perspective. Higher operating frequency requirements further complicate design closure. Semiconductor packages are a quintessential piece of the signal integrity puzzle.
This article addresses the basics of packaging such as types of packages and their advantages and disadvantages, future trends, and factors to be considered while choosing a package.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- An Efficient Device for Forward Collision Warning Using Low Cost Stereo Camera & Embedded SoC
- Testing Of Repairable Embedded Memories in SoC: Approach and Challenges
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 2
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow