A brief primer on embedded SoC packaging options
Deepak Behera, Sumit Varshney, Sunaina Srivastava, and Swapnil Tiwari, Freescale Semiconductor
11/20/2011 9:16 PM EST
With shrinking technology, voltage levels are being reduced, lowering noise margins required to enable a clean design from a signal integrity perspective. Higher operating frequency requirements further complicate design closure. Semiconductor packages are a quintessential piece of the signal integrity puzzle.
This article addresses the basics of packaging such as types of packages and their advantages and disadvantages, future trends, and factors to be considered while choosing a package.
To read the full article, click here
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