Managing design data - consider the whole product
Rob Evans, Altium
EETimes (10/7/2010 10:50 AM EDT)
The idea that electronic product development is becoming more complex each year, or possibly each day, is patently clear to anyone involved in the electronics industry. Electronic products are becoming smaller, cheaper, smarter and more connected, with sophisticated electronic systems making their way into an increasing range of products.
From nuclear power stations to neurological implants, electronics is rapidly becoming a core design element in the quest for greater product functionality and differentiation in an increasingly global electronics market. In the process of making this possible, the number of complex elements that contribute to and influence product designs has also dramatically grown.
Within the electronics design sphere, traditional design capture and board layout has been joined by the development of programmable hardware and embedded application software. The complexity these domains add to the design process is magnified by their interdependence. Even a minor design change in one domain, such as tweaking the pin configuration in the FPGA space, will trigger a rippling series of ECO revisions through the others.
To read the full article, click here
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- Evaluating Data Management Software
- Take control of design data management
- Standardizing data interchanges among design tools in the ECU development process: Pt. 1 - Models, formats, and data management
- Survey shows SoC design data management is mission critical
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection