EDA 3.0: So you are an EDA startup?
By Tom Kozas, President, Energo Design Solutions and Michael Sanie, Managing Director at Maestro International
edadesignline.com (March 17, 2009)
A lot has been written and said in the last few months about the state of the EDA (Electronic Design Automation) industry and how to grow it. Less has been said about EDA startups, their challenges, and growth opportunities.
There is a reason for EDA startups to exist and be supported, namely they have demonstrated a strong advantage in their ability to rapidly implement, deliver, and evolve new technology. Historically new innovation has predominantly come from the startups in this space, but often the new innovation has not turned into successful products and hence profitable businesses. The days of throwing money at startups and hoping they succeed are long past. Startups, their founders, executives, and investors need to take a more strategic approach, ideally before any code is written, but certainly before any significant investment occurs.
edadesignline.com (March 17, 2009)
A lot has been written and said in the last few months about the state of the EDA (Electronic Design Automation) industry and how to grow it. Less has been said about EDA startups, their challenges, and growth opportunities.
There is a reason for EDA startups to exist and be supported, namely they have demonstrated a strong advantage in their ability to rapidly implement, deliver, and evolve new technology. Historically new innovation has predominantly come from the startups in this space, but often the new innovation has not turned into successful products and hence profitable businesses. The days of throwing money at startups and hoping they succeed are long past. Startups, their founders, executives, and investors need to take a more strategic approach, ideally before any code is written, but certainly before any significant investment occurs.
To read the full article, click here
Related Semiconductor IP
- Secure Boot Loader
- Memory Subsystem
- 4/8-bit mixed-precision NPU IP
- Compiler-centric single-core LPU
- SMC 2nm 1V8 ESD Power Clamp – Low Leakage
Related Articles
- Map drives EDA vendors
- EDA leaders trade places
- Chip IP revenues fall, but overall EDA remains healthy in Q1, says group
- Pricing, expansion keys to growth in EDA
Latest Articles
- Versat-AI: An ONNX-to-SoC Compiler for Model-Agnostic CGRA Edge Inference
- HyNoC: A Hybrid Circuit-Switch/Wormhole Network-on-Chip for Distributed VLIW Computing on FPGA
- Hybrid ASIC-FPAA Fabric for Performance Security Trade-off
- A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection