Early Interactive Short Isolation for Faster SoC Verification
By Ritu Walia, Siemens (December 4, 2024)
In modern semiconductor design, shrinking technology nodes and increasing circuit complexity make layout versus schematic (LVS) verification more challenging. One of the most common and critical errors designers find during LVS runs is shorted nets. Identifying and isolating these shorts early in the process is essential to meeting deadlines and ensuring a high-quality design. However, finding shorts in early design cycles can be a time-consuming and resource-intensive task because the design is “dirty” with numerous shorted nets.
To tackle this challenge, designers need a robust LVS solution to address shorts early in the design flow. This article explores common short isolation challenges and presents a novel solution that integrates LVS runs with a powerful debug environment for faster and more efficient verification.
Design size, component density, and advanced nodes like 5 nm and below all contribute to the growing complexity of SoC designs. With layouts containing billions of transistors, connectivity issues like shorted nets can proliferate. Shorts can occur between power/ground networks or signal lines and may result from misalignment, incorrect placement, or simply the close proximity of electrical connections in densely packed areas of the chip.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- Interconnect (NoC) verification in SoC design
- Shifting Mindsets: Static Verification Transforms SoC Design at RT Level
- Efficient methodology for verification of Dynamic Frequency Scaling of clocks in SoC
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs