Designing An ARM-Based Multithreaded Video/Audio/ Motion Recording System - Part 2
Oct 23 2006 (0:30 AM), Embedded.com
[Editor's Note: In Part 1, the author described the basic physical parameters of a video/audio/motion recording system (VAM) and the basic hardware and software building blocks that will be needed before actual implementation and programming of the application.]
Our implementation will be simplified because we are primarily interested in developing a control structure for this system. Thus, we will omit all file handling details, represent files as arrays, and simulate capture of data once per second. (An actual implemented system would capture data about 20 to 40 times per second.) For convenience, we will represent each clock timer-tick as one second.
For this system, we will display information on the screen to show when events are generated and how they are processed. We will also display summary information on a periodic basis. Figure 15 below contains sample diagnostic output for our system that we could use during development.
To read the full article, click here
Related Semiconductor IP
- UALink 200G v1.0 Verification IP
- CCSDS SCCC Demapper and Turbo Decoder
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
Related Articles
- Designing with ARM Cortex-M based SoC Achitectures: Part 2 - Some typical applications
- Designing An ARM-Based Multithreaded Audio/Visual/Motion Recording System: Part 1
- An architecture for designing reusable embedded systems software, Part 2
- Providing memory system and compiler support for MPSoc designs: Customization of memory architectures (Part 2)
Latest Articles
- Anechoic: Onsager-Corrected Parallel Annealing for Sub-0.1 ms Dense Max-Cut on an FPGA
- Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study
- Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
- A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
- An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC