Designing An ARM-Based Multithreaded Video/Audio/ Motion Recording System - Part 2
Oct 23 2006 (0:30 AM), Embedded.com
[Editor's Note: In Part 1, the author described the basic physical parameters of a video/audio/motion recording system (VAM) and the basic hardware and software building blocks that will be needed before actual implementation and programming of the application.]
Our implementation will be simplified because we are primarily interested in developing a control structure for this system. Thus, we will omit all file handling details, represent files as arrays, and simulate capture of data once per second. (An actual implemented system would capture data about 20 to 40 times per second.) For convenience, we will represent each clock timer-tick as one second.
For this system, we will display information on the screen to show when events are generated and how they are processed. We will also display summary information on a periodic basis. Figure 15 below contains sample diagnostic output for our system that we could use during development.
To read the full article, click here
Related Semiconductor IP
- Link Acceleration Unit
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
- Verification IP for eUSB 2 v2 and USB 2.0
Related Articles
- Designing with ARM Cortex-M based SoC Achitectures: Part 2 - Some typical applications
- Designing An ARM-Based Multithreaded Audio/Visual/Motion Recording System: Part 1
- An architecture for designing reusable embedded systems software, Part 2
- Providing memory system and compiler support for MPSoc designs: Customization of memory architectures (Part 2)
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing