Designing a low-cost, low-power multicore ARM-based AV player
Anand Kulkarni, Atria Logic
embedded.com (February 02, 2017)
Low power system design has become a mandatory requirement not only for hand-held mobile devices but also for automotive infotainment systems. Furthermore, automotive systems need to be able to carry the user experience in the home and office over to the car. This increasing demand for high computation, high quality and low power solutions has forced embedded computing to turn to multicore systems. Consequently, embedded solutions based on multicore platforms have become common for many applications such as gaming, video, and image-processing in areas such as mobile, automotive, medical and industrial applications.
The challenge is to utilize multicore based system with available media frameworks that offer scalability of open source access and portability to achieve requirements for low-power, high-performance embedded applications. With the advent of powerful software and hardware programmable system-on-chip (SoC) FPGA devices, embedded system designers are able to design solutions to an exact form, function and performance fit for the requirements of the customer. These solutions are optimal, efficient, cost-effective addressing end customer requirements. The Xilinx Zynq SoC family of FPGAs is such a device.
This article describes the use of a low-cost, low-density Zynq FPGA in creating a computational platform for implementing infotainment systems for passenger vehicles, such as cars, buses, trains, airplanes and ships. Other applications for this kind of platform include digital signage and information displays in private and public venues such as hotels, hospitals, gas pumps, or kiosks as well as digital picture frames for consumer markets.
To read the full article, click here
Related Semiconductor IP
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
- Verification IP for eUSB 2 v2 and USB 2.0
- AFDX 1G Switch IP
Related Articles
- Designing a high-performance, low-cost switch fabric chip-set using COT
- Designing An ARM-Based Multithreaded Audio/Visual/Motion Recording System: Part 1
- Designing An ARM-Based Multithreaded Video/Audio/ Motion Recording System - Part 2
- Designing low-power multiprocessor chips
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing