Design planning for large SoC implemention at 40nm - Part 3
Bhupesh Dasila
EDN (August 9, 2013)
[Part 1 explores the process technology to learn its capabilities and limitations, including evaluating the technology libraries, determining the implementation tools and flows, and capturing the SoC requirements.
Part 2 covers comprehensive planning for complex designs at lower geometry.]
Floorplanning and PnR
A thorough exercise during physical architecture is the foundation for an efficient floorplan. It helps in reducing the overall turnaround time of the physical design phase. The broader prospective of the floorplan should be performed during the physical architecture phase, and the actual floorplaning phase should address the finer details of the floorplan, which impacts the physical design’s QoR.
Floorplanning guidelines
The seed for a floorplan primarily comes from physical architecture, die size-power estimation exercise and the technology. When creating a floorplan, it’s important to consider some basic characteristics of the process technology. The designer should have explored the technology enough in the context of metal stack and metal configuration. Also the designer should have gained ample experience about the availability of vertical and horizontal routing resources and their requirements for the design as per the physical architecture.
At any level, creating “non-preferred” routing (i.e. not using the preferred routing direction for that level) is not recommended. In the case of a channel-based floorplan, when placing blocks, four-way intersections in top-level channels should be avoided; “T” intersections create much less congestion. This consideration can be critical in leaving adequate space for routing channels, especially if there is not much opportunity for over-the-cell routing. Using fly lines can help determine optimal placement and orientation, but when the fly lines are numerous enough to “paint the area” between blocks, designers must rely on their best judgment for block placement, and later evaluate the results for possible modification.
To read the full article, click here
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related Articles
- Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success
- Design planning for large SoC implementation at 40nm - Part 2
- Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
Latest Articles
- CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research
- Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs